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lcamtuf's avatar

Just for fun: a reader on Mastodon pointed me to https://github.com/olofk/serv, which is an attempt to implement a RISC-V CPU using the absolute minimum number of... well, things. I think their goal is to optimize FPGA implementations with LUTs and flip-flops, but they also have a CMOS estimate of 2,100 gates.

This is within the ballpark of what's still realistically possible with relay logic, so one could build a dreadfully slow RISC-V relay computer.

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Jan Szumiec's avatar

Any chance you could share the PCB?

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