Having used all sizes of AVRs in the past and also struggled to clock out timing sensitive data on an RPi I’m enjoying the series! Also very happy to have come across your Substack. Long time fan after your inspirational articles on DIY mould milling and getting all the air bubbles as the epoxy sets.
It is probably worth noting that the SPI bus is ancient - dating back to 1979 - so it acquired a couple of flavors that are rarely encountered today, but might crop up in some contexts, including as a source of confusion in various tutorials and reference docs.
The first SPI variation is clock phase (CPHA). Normal phase means that serial lines are read on the leading edge of a clock cycle, as shown on the figure in the article. Shifted phase means that the data is latched on the tailing edge. Again, this is uncommon in modern-day chips.
The second variation is clock polarity (CPOL). Again, normal polarity is that the clock idles at 0V and goes high and then back down with every tick. Reverse polarity has the clock idling at high.
SPI controllers default to CPHA=0 and CPOL=0., and this is known as "mode 0". Shifted phase (CPHA=1) is known as "mode 1". Inverted clock (CPOL=1) is known as "mode 2". A combination of the two is "mode 3".
Also, for the curious: "MISO" stands for "master in slave out" and "MOSI" stands for "master out slave in". Putting aside the nowadays slightly controversial nomenclature, the mnemonics are rather confusing and I try to avoid them whenever I can.
Having used all sizes of AVRs in the past and also struggled to clock out timing sensitive data on an RPi I’m enjoying the series! Also very happy to have come across your Substack. Long time fan after your inspirational articles on DIY mould milling and getting all the air bubbles as the epoxy sets.
It is probably worth noting that the SPI bus is ancient - dating back to 1979 - so it acquired a couple of flavors that are rarely encountered today, but might crop up in some contexts, including as a source of confusion in various tutorials and reference docs.
The first SPI variation is clock phase (CPHA). Normal phase means that serial lines are read on the leading edge of a clock cycle, as shown on the figure in the article. Shifted phase means that the data is latched on the tailing edge. Again, this is uncommon in modern-day chips.
The second variation is clock polarity (CPOL). Again, normal polarity is that the clock idles at 0V and goes high and then back down with every tick. Reverse polarity has the clock idling at high.
SPI controllers default to CPHA=0 and CPOL=0., and this is known as "mode 0". Shifted phase (CPHA=1) is known as "mode 1". Inverted clock (CPOL=1) is known as "mode 2". A combination of the two is "mode 3".
Also, for the curious: "MISO" stands for "master in slave out" and "MOSI" stands for "master out slave in". Putting aside the nowadays slightly controversial nomenclature, the mnemonics are rather confusing and I try to avoid them whenever I can.