9 Comments
3dEdited

And yep, before someone chimes in with the same recommendation: Rick Hartley has some great in-depth videos and presentations that do this topic more justice. That said, I think they are less accessible; and most importantly, I think they're difficult to interpret in context. Designing PC motherboards or Starlink terminals is not the same as building AVR blinkenlights.

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Eric Bogatin (search for his articles and videos) is another highly recommendable source in terms of signal integrity and RF-PCB-design.

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There's another disadvantage to copper pours, when dealing with high power circuits then a significant voltage drop can be created across the whole board, resulting in different component's having a different idea of what ground is. This is a problem if you're trying to measure low frequency signals (sub MHz-ish) at milli- or micro-volt levels on the same board that handles high currents (Amps).

Such circuits can actually perform better if you isolate part of the pour, or route a dedicated small signal ground, connecting to the pour at a single point.

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This article brings me back to the many many hours of routing in Altium early in my career!

One strategy I remember using to deal with a broken ground plane was using a matrix of vias to "stitch" the ground plane of the top layer and ground layer together. Or, in your final example, you could place a Vdd plane on the bottom layer, and add a line of vias at the top edge of the board.

As a non-practicing ECE I know there are electrical tradeoffs to this approach, but I'm not qualified to comment on them anymore.

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In that first diagram, when the frequency increases, does the path along the backplane that mirrors the trace automatically become the lowest-resistance path, and the path of highest current?

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Those last two example images are rather opaque for beginners. Could you spell out what’s wrong with them?

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The idea is that for the reasons discussed earlier, if you have a high-frequency signal, the lowest-impedance return path is generally next to the "forward" path, possibly on the opposite side of the PCB. Copper pours and ground planes are a cheap way to provide a conforming return path from any point in the circuit.

But in the first image, that return current on the back (blue) layer can't cling onto the outline of the front (red) traces, because there is a non-conductive gap created to accommodate some other signal crossing perpendicularly. Electrons can't jump the gap, so impedance becomes higher.

As for the second image, the intent was to use copper pours to provide convenient hook up to GND and Vdd anywhere in the circuit, so that you don't need to explicitly route power traces. But because of the layout of other traces on the top layer, the path to the Vdd pin of the chip (top right) is needlessly long and narrow, hugging the edge of the board. You could even imagine a more extreme example where some portion of the power plane is completely cordoned off, although PCB design software should detect that and complain.

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Thank you. I had understood the first, but in the second I has mis-guessed that they _accidentally_ connected Vdd to the copper pour.

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I have enough challenge with my simple single sided boards, some have pours, a few jumpers. Did a lot of wire wrap. See vertical stuff and point to point, island cutters etc.. Impressed with elegant creativity of bright engineers and powerful software too.

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